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NOC:Hardware modeling using verilog
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NOC:Hardware modeling using verilog
by Prof Indranil Sengupta

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of geneti...

0.0  (0 Ratings) 1449 Learner
validy img Validity Unlimited
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level English
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Program Fee
FREE
About This Course

Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of geneti...

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Course Curriculum
8 Sections | 41 Lecture | 20h 47min total length
Expand all sections
NOC:Hardware modeling using verilog

Week 1

| 02h 23min total length
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    Lecture 5:

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    Lecture 4:

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    Lecture 3:

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    Lecture 2:

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    Lecture 1:

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NOC:Hardware modeling using verilog

Week 2

| 03h 20min total length
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    Lecture 6: VERILOG LANGUAGE FEATURES (PART 1)

    31m <?php echo $alt; ?>
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    Lecture 7: VERILOG LANGUAGE FEATURES (PART 2)

    33m <?php echo $alt; ?>
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    Lecture 8: VERILOG LANGUAGE FEATURES (PART 3)

    27m <?php echo $alt; ?>
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    Lecture 9: VERILOG OPERATORS

    36m <?php echo $alt; ?>
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    Lecture 10:VERILOG MODELING EXAMPLES

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    Lecture 11: VERILOG MODELING EXAMPLES (Contd)

    36m <?php echo $alt; ?>
NOC:Hardware modeling using verilog

Week 3

| 02h 09min total length
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    Lecture 12: VERILOG DESCRIPTION STYLES

    29m <?php echo $alt; ?>
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    Lecture 13: PROCEDURAL ASSIGNMENT

    30m <?php echo $alt; ?>
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    Lecture 14: PROCEDURAL ASSIGNMENT (Contd.)

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    Lecture 15: PROCEDURAL ASSIGNMENT (EXAMPLES)

    37m <?php echo $alt; ?>
NOC:Hardware modeling using verilog

Week 4

| 02h 22min total length
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    Lecture 17:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)

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    Lecture 17: BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 2)

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    Lecture 18:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 3)

    25m <?php echo $alt; ?>
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    Lecture 19:BLOCKING / NON-BLOCKING ASSIGNMENTS (PART 4)

    25m <?php echo $alt; ?>
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    Lecture 20:USER DEFINED PRIMITIVES

    31m <?php echo $alt; ?>
NOC:Hardware modeling using verilog

Week 5

| 02h 13min total length
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    Lecture 21 : VERILOG TEST BENCH

    28m <?php echo $alt; ?>
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    Lecture 22 : WRITING VERILOG TEST BENCHES

    33m <?php echo $alt; ?>
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    Lecture 23 : MODELING FINITE STATE MACHINES

    35m <?php echo $alt; ?>
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    Lecture 24 : MODELING FINITE STATE MACHINES (Contd.)

    35m <?php echo $alt; ?>
NOC:Hardware modeling using verilog

Week 6

| 02h 46min total length
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    Lecture 29 : SOME RECOMMENDED PRACTICES

    33m <?php echo $alt; ?>
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    Lecture 28 : SYNTHESIZABLE VERILOG

    33m <?php echo $alt; ?>
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    Lecture 27: DATAPATH AND CONTROLLER DESIGN (PART 3)

    33m <?php echo $alt; ?>
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    Lecture 26 : DATAPATH AND CONTROLLER DESIGN (PART 2)

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    Lecture 25 : DATAPATH AND CONTROLLER DESIGN (PART 1)

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NOC:Hardware modeling using verilog

Week 7

| 03h 01min total length
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    Lecture 36: SWITCH LEVEL MODDELING (PART 2)

    25m <?php echo $alt; ?>
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    Lecture 35: SWITCH LEVEL MODELING (PART 1)

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    Lecture 34: PIPELINE MODELING (PART 2)

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    Lecture 33: PIPELINE MODELING (PART 1)

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    Lecture 32: BASIC PIPELINING CONCEPTS

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    Lecture 31: MODELING REGISTER BANKS

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    Lecture 30: MODELING MEMORY

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NOC:Hardware modeling using verilog

Week 8

| 02h 30min total length
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    Lecture 41 : VERILOG MODELING OF THE PROCESSOR (PART 2)

    30m <?php echo $alt; ?>
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    Lecture 40 : VERILOG MODELING OF THE PROCESSOR (PART 1)

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    Lecture 39 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 3)

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    Lecture 38 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 2)

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    Lecture 37 : PIPELINE IMPLEMENTATION OF A PROCESSOR (PART 1)

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show 5 more sections
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