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Advanced VLSI Design

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Advanced VLSI Design

Validity Unlimited Advanced VLSI Design All Level Advanced VLSI Design English

4.0 (1)
Free

About This Course

Historical Perspective of VLSI, CMOS VLSI Design for Power and Speed consideration, Logical Efforts: Designing Fast CMOS Circuits; Datapath Design, Interconnect aware design, Hardware Description Languages for VLSI Design, FSM Controller/Datapath and Processor Design, VLSI Design Automation, and VLSI Design Test and Verification.

  • Advanced VLSI Design Total 1 Module
  • Advanced VLSI Design 42 Videos
  • Advanced VLSI Design Downloadable on mobile
  • Advanced VLSI Design Published on 26 June, 2019

Course Curriculum

Advanced VLSI Design

Advanced VLSI Design
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    L1-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design

    53m <?php echo  $alt; ?>
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    L2-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design - Part II

    1h 102 min <?php echo  $alt; ?>
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    L3-Logical Effort - A way of Designing Fast CMOS Circuits

    1h 66 min <?php echo  $alt; ?>
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    L4-Logical Effort - A way of Designing Fast CMOS Circuits continued?

    1h 72 min <?php echo  $alt; ?>
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    L5-Logical Effort - A way of Designing Fast CMOS Circuits -Part III

    1h 75 min <?php echo  $alt; ?>
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    L6-Power Estimation and Control in CMOS VLSI circuits

    1h 60 min <?php echo  $alt; ?>
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    L7-Power Estimation and Control in CMOS VLSI circuits continued

    1h 79 min <?php echo  $alt; ?>
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    L8-Low Power Design Techniques

    54m <?php echo  $alt; ?>
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    L9-Low Power Design Techniques -Part II

    1h 111 min <?php echo  $alt; ?>
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    L10-Arithmetic Implementation Strategies for VLSI

    57m <?php echo  $alt; ?>
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    L11-Arithmetic Implementation Strategies for VLSI -Part II

    59m <?php echo  $alt; ?>
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    L12-Arithmetic Implementation Strategies for VLSI -Part III

    1h 109 min <?php echo  $alt; ?>
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    L13-Arithmetic Implementation Strategies for VLSI -Part IV

    1h 95 min <?php echo  $alt; ?>
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    L14-Interconnect aware design: Impact of scaling, buffer insertion and inductive peaking

    53m <?php echo  $alt; ?>
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    L15-Interconnect aware design: Low swing and Current mode signaling

    53m <?php echo  $alt; ?>
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    L16-Interconnect aware design: capacitively coupled interconnects

    49m <?php echo  $alt; ?>
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    L17-Introduction to Hardware Description Languages

    51m <?php echo  $alt; ?>
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    L18-Managing concurrency and time in Hardware Description Languages

    53m <?php echo  $alt; ?>
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    L19-Introduction to VHDL

    52m <?php echo  $alt; ?>
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    L20-Basic Components in VHDL

    51m <?php echo  $alt; ?>
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    L21-Structural Description in VHDL

    52m <?php echo  $alt; ?>
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    L22-Behavioral Description in VHDL

    51m <?php echo  $alt; ?>
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    L23-Introduction to Verilog

    51m <?php echo  $alt; ?>
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    L24-FSM datapath (GCD example)

    58m <?php echo  $alt; ?>
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    L25-FSM datapath (continued)

    54m <?php echo  $alt; ?>
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    L26-Single Cycle MMIPS

    54m <?php echo  $alt; ?>
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    L27-Multicycle MMIPS

    1h 76 min <?php echo  $alt; ?>
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    L28-Multicycle MMIPS? FSM

    1h 81 min <?php echo  $alt; ?>
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    L29-Brief Overview of Basic VLSI Design Automation Concepts

    1h 61 min <?php echo  $alt; ?>
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    L30-Netlist and System Partitioning

    1h 62 min <?php echo  $alt; ?>
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    L31-Timing Analysis in the context of Physical Design Automation

    1h 65 min <?php echo  $alt; ?>
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    L32-Placement algorithm

    48m <?php echo  $alt; ?>
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    L33-Introduction to VLSI Testing

    56m <?php echo  $alt; ?>
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    L34-VLSI Test Basics - I

    59m <?php echo  $alt; ?>
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    L35-VLSI Test Basics - II

    58m <?php echo  $alt; ?>
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    L36-VLSI Testing: Automatic Test Pattern Generation

    55m <?php echo  $alt; ?>
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    L37-VLSI Testing: Design for Test (DFT)

    56m <?php echo  $alt; ?>
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    L38-VLSI Testing: Built-In Self-Test (BIST)

    58m <?php echo  $alt; ?>
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    L39-VLSI Design Verification: An Introduction

    54m <?php echo  $alt; ?>
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    L40-VLSI Design Verification: An Introduction

    52m <?php echo  $alt; ?>
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    L41-VLSI Design Verification: Equivalence/Model Checking

    50m <?php echo  $alt; ?>
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    L42-VLSI Design Verification: Model Checking

    1h 60 min <?php echo  $alt; ?>

Review & Ratings

4.0

1 Ratings

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https://study247.s3-accelerate.amazonaws.com/studyx

dipshika shrivastava

22 Feb 2021 01:45 PM

Very Good

Thankyou Prof A.N. Chandorkar for this wonderful course

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Advanced VLSI Design Advanced VLSI Design Comment

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