In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architect...
In computer engineering, computer architecture is a set of rules and methods that describe the functionality, organization, and implementation of computer systems. Some definitions of architecture define it as describing the capabilities and programming model of a computer but not a particular implementation. In other definitions computer architect...
Lecture 1 : Evolution of Computer Systems
34mLecture 5 : Instruction Set Architecture?
38mLecture 4 : Software and Architecture Types
38mLecture 3 : Memory Addressing and Languages
38mLecture 2 : Basic Operation of a Computer
38mLecture 10 MIPS Programming Examples
32mLecture 9 : MIPS32 Instruction Set
32mLecture 8 : CISC and RISC Architecture
32mLecture 7 : Instruction Format and Addressing Modes
32mLecture 6 : Number Representation
32mLecture 13 : CHOICE OF BENCHMARKS
32mLecture 12 : MEASURING CPU PERFORMANCE
32mLecture 14 : SUMMARIZING PERFORMANCE RESULTS
21mLecture 15 : AMADAHL LAW (PART 1)
29mLecture 16 : AMADAHL LAW (PART 2)
27mLecture 18 :DESIGN OF CONTROL UNIT (PART 2)
35mLecture 17 : DESIGN OF CONTROL UNIT (PART 1)
35mLecture 19 : DESIGN OF CONTROL UNIT (PART 3)
20mLecture 20 : DESIGN OF CONTROL UNIT (PART 4)
27mLecture 21 : MIPS IMPLEMENTATION (PART 1)
27mLecture 22 : MIPS IMPLEMENTATION (PART 2)
26mLecture 23? PROCESSOR MEMORY INTERACTION
31mLecture 24 : STATIC AND DYNAMIC RAM
32mLecture 25 : ASYNCHRONOUS DRAM
32mLecture 26 : SYNCHRONOUS DRAM
26mLecture 27 :MEMORY INTERFACING AND ADDRESSING
33mLecture 28 : MEMORY HIERARCHY DESIGN (PART 1)
41mLecture 29 : MEMORY HIERARCHY DESIGN (PART 2)
28mLecture 30 : CACHE MEMORY (PART 1)
48mLecture 31 : CACHE MEMORY (PART 2)
30mLecture 32 : IMPROVING CACHE PERFORMANCE
39mLecture 33 : DESIGN OF ADDERS (PART 1)
35mLecture 34 : DESIGN OF ADDERS (PART 2)
33mLecture 37 : DESIGN OF DIVIDERS
46mLecture 36 : DESIGN OF MULTIPLIERS (PART 2)
46mLecture 35 : DESIGN OF MULTIPLIERS (PART 1)
46mLecture 42 : ARITHMETIC PIPELINE
24mLecture 41 : PIPELINE SCHEDULING
24mLecture 40 : BASIC PIPELINING CONCEPTS
24mLecture 39 : FLOATING-POINT ARITHMETIC
24mLecture 38 : FLOATING-POINT NUMBERS
24mLecture 47 : INTERRUPT HANDLING (PART 2)
27mLecture 46 : INTERRUPT HANDLING (PART 1)
27mLecture 45 : DATA TRANSFER TECHNIQUES
27mLecture 44 : INPUT-OUTPUT ORGANIZATION
27mLecture 43 : SECONDARY STORAGE DEVICES
27mLecture 52 : BUS STANDARDS
31mLecture 51 : BUS STANDARDS
31mLecture 50: EXERCISES ON I/O TRANSFER
31mLecture 49 : SOME EXAMPLE DEVICE INTERFACING
31mLecture 48 : DIRECT MEMORY ACCESS
31mLecture 58: PIPELINE HAZARDS (PART 4)
33mLecture 57: PIPELINE HAZARDS (PART 3)
33mLecture 56: PIPELINE HAZARDS (PART 2)
33mLecture 55: PIPELINE HAZARDS (PART 1)
33mLecture 54: MIPS PIPELINE (Contd.)
33mLecture 53: PIPELINING THE MIPS32 DATA PATH?
33mLecture 64 : SUMMARIZATION OF THE COURSE
26mLecture 63 : SOME CASE STUDIES
26mLecture 62: MULTI-CORE PROCESSORS
26mLecture 61 : VECTOR PROCESSORS
26mLecture 60 : EXPLOITING INSTRUCTION LEVEL PARALLELISM
26mLecture 59 : MULTICYCLE OPERATIONS IN MIPS32
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