Switching circuit theory is the mathematical study of the properties of networks of idealized switches. Such networks may be strictly combinational logic, in which their output state is only a function of the present state of their inputs; or may also contain sequential elements, where the present state depends on the present state and past states;...
Switching circuit theory is the mathematical study of the properties of networks of idealized switches. Such networks may be strictly combinational logic, in which their output state is only a function of the present state of their inputs; or may also contain sequential elements, where the present state depends on the present state and past states;...
Lecture 06: Error Detection and Correction
27mLecture 05: BCD and Gray Code Representations
27mLecture 04: Binary Addition and Subtraction
27mLecture 03: Signed and Unsigned Binary Number Representation
27mLecture 02: Octal and Hexadecimal Number Systems
27mLecture 01: Introduction
27mLecture 10: Emerging Technologies (Part II)
21mLecture 09: Emerging Technologies (Part I)
21mLecture 08: Logic Families to Implement Gates
21mLecture 07: Logic Gates
21mLecture 15 : Functional Completeness
35mLecture 14 : Obtaining Canonical Representations of Functions
35mLecture 13 : Properties of Switching Functions
35mLecture 12 : Algebraic Manipulation
35mLecture 11 : Switching Algebra
35mLecture 16: Minimization Using Karnaugh Maps (Part I)
27mLecture 17: Minimization Using Karnaugh Maps (Part II)
27mLecture 21: Design of Adders (Part I)
27mLecture 22: Design of Adders (Part II)
33mLecture 23: Design of Adders (Part III)
33mLecture 24: Logic Design(Part I)
35mLecture 25: Logic Design(Part II)
29mLecture 26: Logic Design(Part III)
32mLecture 30: Threshold Logic and Threshold Gates
32mLecture 29: Logic Design using AND-EXOR Network
32mLecture 28: Binary Decision Diagrams (Part II)
32mLecture 27: Binary Decision Diagrams (Part I)
32mLecture 31: Latches and Flip-Flops (Part I)
30mLecture 32: Latches and Flip-Flops (Part II)
30mLecture 33: Latches and Flip-Flops (Part III)
31mLecture 34: Clocking and Timing (Part I)
31mLecture 35: Clocking and Timing (Part II)
31mLecture 36: Synthesis of Synchronous Sequential Circuits (Part I)
30mLecture 37: Synthesis of Synchronous Sequential Circuits (Part II)
30mLecture 40: Minimization of Finite State Machines (Part I)
30mLecture 39: Synthesis of Synchronous Sequential Circuits (Part IV)
30mLecture 38: Synthesis of Synchronous Sequential Circuits (Part III)
30mLecture 46: Design of Counters (Part II)
26mLecture 45: Design of Counters (Part I)
26mLecture 44: Design of Registers (Part III)
26mLecture 43: Design of Registers (Part II)
26mLecture 42: Design of Registers (Part I)
26mLecture 51: Analog-to-Digital Converter (Part III)
25mLecture 50: Analog-to-Digital Converter (Part II)
25mLecture 49: Analog-to-Digital Converter (Part I)
25mLecture 48: Digital-to-Analog Converter (Part II)
25mLecture 47: Digital-to-Analog Converter (Part I)
25mLecture 54: Algorithmic State Machine (ASM) Chart
21mLecture 53: Asynchronous Sequential Circuits (Part II)
21mLecture 52: Asynchronous Sequential Circuits (Part I)
21mLecture 57 : Test Pattern Generation
28mLecture 56 : Fault Modeling
28mLecture 55 : Testing of Digital Circuits
28mLecture 58 : Design for Testability
22mLecture 59 : Built-in Self-Test (Part I)
27mLecture 60 : Built-in Self-Test (Part II)
21m