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NOC:VLSI Physical Design
broucher Course Brochure
NOC:VLSI Physical Design
by Prof Indranil Sengupta

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ...

5.0  (870 Ratings) 1296 Learner
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level All Level
level English
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Program Fee
FREE
About This Course

In integrated circuit design, physical design is a step in the standard design cycle which follows after the circuit design. At this step, circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ...

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Course Curriculum
12 Sections | 64 Lecture | 31h 44min total length
Expand all sections
NOC:VLSI Physical Design

Week 1

| 02h 51min total length
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    Lecture 6: VLSI Physical Design Automation (Part 2)

    28m <?php echo $alt; ?>
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    Lecture 5: VLSI Physical Design Automation (Part 1)

    28m <?php echo $alt; ?>
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    Lecture 4: VLSI Design Styles (Part 2)

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    Lecture 3: VLSI Design Styles (Part 1)

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    Lecture 2: Design Representation

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    Lecture 1: Introduction

    28m <?php echo $alt; ?>
NOC:VLSI Physical Design

Week 2

| 04h 06min total length
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    Lecture 8: Floorplanning

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    Lecture 7: Partitioning

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    Lecture 14: Placement (Part 4)

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    Lecture 13: Placement (Part 3)

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    Lecture 12: Placement (Part 2)

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    Lecture 11: Placement (Part 1)

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    Lecture 10: Pin Assignment

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    Lecture 9: "Floorplanning Algorithms

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NOC:VLSI Physical Design

Week 3

| 02h 31min total length
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    Lecture 19: Global Routing (Part 2)

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    Lecture 18: Global Routing (Part 1)

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    Lecture 17: Grid Routing (Part 3)

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    Lecture 16: Grid Routing (Part 2)

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    Lecture 15: Grid Routing (Part 1)

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NOC:VLSI Physical Design

Week 4

| 03h 20min total length
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    Lecture 26 : Clock Design (Part 3)

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    Lecture 25 : Clock Design (Part 2)

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    Lecture 23 : Detailed Routing (Part 4)

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    Lecture 24 : Clock Design (Part 1)

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    Lecture 21: Detailed Routing (Part 2)

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    Lecture 22: Detailed Routing (Part 3)

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    Lecture 20 : Detailed Routing (Part 1)

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NOC:VLSI Physical Design

Week 5

| 02h 24min total length
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    Lecture 31: POWER AND GROUND ROUTING

    34m <?php echo $alt; ?>
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    Lecture 30: CLOCK NETWORK SYNTHESIS (PART 4)

    27m <?php echo $alt; ?>
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    Lecture 29: CLOCK NETWORK SYNTHESIS (PART 3)

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    Lecture 28: CLOCK NETWORK SYNTHESIS (PART 2)

    27m <?php echo $alt; ?>
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    Lecture 27: CLOCK NETWORK SYNTHESIS (PART 1)

    27m <?php echo $alt; ?>
NOC:VLSI Physical Design

Week 6

| 02h 56min total length
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    Lecture 36: Time Closure (Part 5)

    29m <?php echo $alt; ?>
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    Lecture 37: Timing Driven Placement

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    Lecture 35: Time Closure (Part 4)

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    Lecture 34: Time Closure (Part 3)

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    Lecture 33: Time Closure (Part 2)

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    Lecture 32: Time Closure (Part 1)

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NOC:VLSI Physical Design

Week 7

| 02h 41min total length
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    Lecture 42 : Miscellaneous Approaches to Timing Optimization?

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    Lecture 41: Performance-Driven Design Flow

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    Lecture 40 : Physical Synthesis (Part 2)

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    Lecture 39: Physical Synthesis (Part 1)

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    Lecture 38: Timing Driven Routing

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NOC:VLSI Physical Design

Week 8

| 02h 49min total length
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    Lecture 47 : Layout Compaction (Part 2)

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    Lecture 46 : Layout Compaction (Part 1)

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    Lecture 45 : Design Rule Check

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    Lecture 44 : Interconnect Modeling (Part 2)

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    Lecture 43 :Interconnect Modeling (Part 1)

    33m <?php echo $alt; ?>
NOC:VLSI Physical Design

Week 9

| 02h 35min total length
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    Lecture 52 :

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    Lecture 51 :

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    Lecture 50 :

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    Lecture 49 :

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    Lecture 48 :

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NOC:VLSI Physical Design

Week 10

| 02h 11min total length
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    Lecture 53 : Test Pattern Generation

    28m <?php echo $alt; ?>
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    Lecture 54: Design for Testability

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    Lecture 55: Boundary Scan Standard

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    Lecture 56: Built-in Self-Test (Part 1)

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    Lecture 57: Built-in Self-Test (Part 2)

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NOC:VLSI Physical Design

Week 11

| 02h 05min total length
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    Lecture 61 : Gate Level Design for Low Power (Part 2)

    31m <?php echo $alt; ?>
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    Lecture 60 : Gate Level Design for Low Power (Part 1)

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    Lecture 59 : Techniques to Reduce Power

    31m <?php echo $alt; ?>
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    Lecture 58 : Low Power VLSI Design

    31m <?php echo $alt; ?>
NOC:VLSI Physical Design

Week 12

| 01h 10min total length
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    Lecture 62 : Other Low Power Design Techniques

    24m <?php echo $alt; ?>
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    Lecture 63 : Algorithmic Level Techniques for Low Power Design

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    Lecture 64 : Summarization of the Course

    14m <?php echo $alt; ?>
show 9 more sections

Review & Ratings

5.0
https://img1.study24x7.com/assets/images/svg-three/course/courseDetails/videoPlayIcon.svg

Preeti Mishra

12 Sep 2023 01:14 PM

Good

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dipshika shrivastava

22 Feb 2021 01:19 PM

good, but some topic were missing

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