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Priya Sharma
Priya Sharma
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Priya Sharma

Studied Master of Science at University of Kota
Live in Kota,India, Rajasthan
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Priya Sharma
24 Apr 2024 11:21 AM study24x7 study24x7

The fixed count that should be used so that the output register will represent the input for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).

A

000110

B

0010

C

1111

D

011101

IIT Entrance IIT-JEE
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Priya Sharma
24 Apr 2024 11:20 AM study24x7 study24x7

The number of distinct Boolean expression of 4 variables is

A

16

B

256

C

1024

D

65536

IIT Entrance IIT-JEE
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Priya Sharma
24 Apr 2024 11:19 AM study24x7 study24x7

The hexadecimal number (3E8)16 is equal to decimal number

A

1000

B

982

C

768

D

323

IIT Entrance IIT-JEE
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Priya Sharma
24 Apr 2024 11:07 AM study24x7 study24x7

A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time

A

8 μ sec

B

10 μ sec

C

2 μ sec

D

5 μ sec

IIT Entrance IIT-JEE
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Priya Sharma
24 Apr 2024 11:04 AM study24x7 study24x7

Zero suppression is not used in actual practice.

A

true

B

false

IIT Entrance IIT-JEE
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Priya Sharma
24 Apr 2024 10:09 AM study24x7 study24x7

In register index addressing mode the effective address is given by

A

index register value

B

sum of the index register value and the operand

C

operand

D

difference of the index register value and the operand

IIT Entrance IIT-JEE
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Priya Sharma
23 Apr 2024 01:34 PM study24x7 study24x7

A carry look ahead adder is frequently used for addition because

A

it costs less

B

it is faster

C

it is more accurate

D

is uses fewer gates

IIT Entrance IIT-JEE
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Priya Sharma
23 Apr 2024 01:33 PM study24x7 study24x7

Which device has one input and many outputs?

A

Multiplexer

B

Demultiplexer

C

Counter

D

Flip flop

IIT Entrance IIT-JEE
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Priya Sharma
23 Apr 2024 01:31 PM study24x7 study24x7

The output of a half adder is

A

SUM

B

CARRY

C

SUM and CARRY

D

none of the above

IIT Entrance IIT-JEE
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Priya Sharma
23 Apr 2024 01:30 PM study24x7 study24x7

A full adder can be made out of

A

two half adders

B

two half adders and a OR gate

C

two half adders and a NOT gate

D

three half adders

IIT Entrance IIT-JEE
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